1. Field of the Invention
The present invention relates to a method of forming apertures in a dielectric layer overlying a substrate of semiconductor material and, more specifically, to a method of forming high aspect ratio contact apertures through doped silicon dioxide using an inductively coupled etcher.
2. State of the Art
The semiconductor industry""s persistence in development efforts to achieve ever-smaller integrated circuitry on the active surfaces of semiconductor substrates consequently necessitates the formation of smaller topographical features defining components of such integrated circuitry. One such feature is the so-called contact aperture, or xe2x80x9ccontact,xe2x80x9d which typically comprises a circular hole extending through a layer of dielectric to a structure formed on or in an underlying semiconductor substrate. As used herein, the term xe2x80x9csemiconductor substratexe2x80x9d encompasses not only traditional, substantially circular wafers of silicon and other materials such as gallium arsenide and indium phosphide, but also semiconductor material (usually, but not exclusively silicon) layers carried on supporting substrates, generally categorized as silicon-on-insulator (SOI) structures, including, without limitation, silicon-on-glass (SOG) and silicon-on-sapphire (SOS) structures.
As circuit component structures, including contacts, enter the sub-half micron range of dimensions, tolerances become more critical and demand more precise process parameters. For example, sub-half micron contacts must hold the top contact diameter, or top CD, within a narrow tolerance band while a high aspect ratio contact is etched through a dielectric layer, and the contact itself must exhibit a substantially cylindrical cross section (i.e., little taper) to achieve an effective contact area with the underlying silicon substrate. As used herein, the term xe2x80x9chigh aspect ratioxe2x80x9d as applied to contact structures is currently contemplated to indicate a depth to width, or diameter, ratio of about five to one or more (xe2x89xa75:1). In addition to contacts, it is also necessary in some instances to etch high aspect ratio sub-half micron width lines or trenches through dielectric layers, and fabrication of these structures demands similar precision.
So-called xe2x80x9cdryxe2x80x9d or plasma etches have been the process of choice for forming sub-half micron contacts. Current high density (inductively coupled) etch systems, also commonly referenced as xe2x80x9cetch tools,xe2x80x9d used in manufacturing of integrated circuits are new to the wafer fabrication industry and are still viewed as both difficult and expensive to operate. There is a need in the industry for simpler processes to use in the operation of these etch tools.
For example, it would be highly desirable to etch high aspect ratio contacts through a layer of doped silicon dioxide such as borophosphosilicate glass, or BPSG, and sometimes through additional layers such as other oxides, silicon nitride or inorganic, dielectric anti-reflective coating (DARC) films between the mask and the substrate silicon. Processing requirements for formation of such contact structures dictate the ability to hold top CD for a 2.2 xcexcm deep feature overetched by 0.4 xcexcm and to generate a contact profile that is vertical or only slightly tapered. A small (less than 0.025 xcexcm) increase in the radius of the feature caused by reentrant profile may be tolerated. Desired contact structures to be achieved would have a minimum nominal depth of 2.2 xcexcm and a top CD of between 0.2 and 0.45 xcexcm, with in-spec top CD and profile control. High selectivity for BPSG to the substrate silicon is required, as is the ability to etch the other films such as the aforementioned silicon nitride and DARC films.
Applied Materials, Inc. of Santa Clara, Calif. currently offers commercially an inductively-coupled plasma etcher identified as the Dielectric Etch IPS Centura(copyright) system (the xe2x80x9cIPS systemxe2x80x9d) for etching high aspect ratio contacts, among other purposes. The IPS system employs an inductively-coupled, parallel plate technology which employs a fluorine scavenger in the form of silicon within the etch chamber in combination with fluorine-substituted hydrocarbon etch gases to achieve an oxide etch having a selectivity to silicon nitride in excess of 10:1. U.S. Pat. No. 5,423,945, assigned to Applied Materials, Inc. discloses the structure and operation of a predecessor apparatus to the IPS system, a schematic of which is shown in FIG. 1.
IPS system 10, as depicted in FIG. 1, includes an etch chamber 12 primarily defined between a grounded silicon roof 14, an RF powered (bias) wafer support 16 and a silicon ring 18 surrounding wafer support or chuck 16, on which wafer 100 is disposed for processing. A plasma 20, generated over wafer 100, is confined by a magnetic field as shown in dotted lines at 22 and 24. Gases are supplied to etch chamber 12 through valved manifold 26, which is connected to a plurality of gas sources (not shown). Evacuation of etch chamber 12 may be effected, as desired, through valve 28, as known in the art. RF source power is supplied to inner antenna 30 and outer antenna 32 by RF generator 34. The antennae 30 and 32 are tuned to resonance for efficient inductive coupling with the plasma 20. Inner antenna 30, outer antenna 32, RF generator 34 and associated circuitry comprise a source network 36. Bias power is also supplied to wafer support 16 by RF generator 34. RF generator 34, supplying power to wafer support 16, comprises a bias network 38 with associated circuitry as shown. RF bias power is delivered at 1.7xc2x10.2 MHz, RF outer antenna power at 2.0xc2x10.1 MHz, and RF inner antenna power at 2.3xc2x10.1 MHz. Other details of the IPS system 10 being entirely conventional, no further discussion thereof is required.
A plasma etch process initially developed for use with the IPS system employs a gas flow of a relatively high rate and somewhat complex chemistry, relatively high process temperatures and, most notably, CO (carbon monoxide) in the gas mixture. Specifically, the process employs 300-400 (and preferably 358) standard cubic centimeters per minute (sccm) Ar (argon), 55 sccm CO, 82 sccm CHF3 (trifluoromethane) and 26 sccm CH2F2 (difluoromethane) with a process pressure of 50 mTorr. Source power input is about 1650 watts, apportioned as 1400 watts to the outer antenna and 250 watts to the inner antenna. Bias power is about 800 watts. According to the IPS system manufacturer, the high volume of Ar is purportedly required, or at least desirable, to maintain a plasma state within the etch chamber. CO is included in the gas mixture used with the IPS system to prevent so-called xe2x80x9cetch stop,xe2x80x9d or the simultaneous and premature cessation of etching during formation of a topographic feature such as a contact. CO is required to suppress etch stop under the relatively high process temperatures employed with the IPS system, notably 145xc2x0 C. roof 14 and 315xc2x0 C. ring 18 temperatures. However, it is known that CO use has caused Nickel (Ni) contamination of the etch chamber. The IPS system may be unusually susceptible to such contamination due to the aforementioned presence of a silicon scavenger material within the system chamber. Further, Ni contamination may degrade etch process performance, and it is also well known that Ni contamination of silicon (i.e., of the wafers disposed in the chamber for etching) may degrade transistor performance and reduce yields. Levels of 1e13Ni atoms/cm**2 have been measured on silicon test wafers etched in a Ni-contaminated IPS system chamber. Consequently, the proven risk of Ni contamination from CO gas is high, and so the proposed CO-laden gas mixture would only be acceptable with the IPS system if no alternative existed. Moreover, the process as now designed for use with the IPS system fails to meet the aforementioned top CD and contact profile requirements. Finally, chamber stability under the foregoing proposed process parameters has yet to be established, as well as the process window.
In short, while the Dielectric Etch IPS Centura(copyright) system shows promise, it has demonstrated notable deficiencies when employed with the process parameters and gas mixture initially proposed for it. Thus, it would be advantageous to develop a process for use with the IPS system which would be simple and easy to control and optimize while still meeting manufacturing specifications for the high aspect ratio contacts (and other apertures, such as lines or trenches) which may be formed therewith. Such a process would be expected to yield similar results in any inductively-coupled plasma etcher which employs silicon surfaces at elevated temperatures within the etch chamber.
Another inductively-coupled plasma etching system, the Lam Research Corporation TCP(trademark) 9100 high-density oxide etch system (the xe2x80x9cTCP systemxe2x80x9d), is also designed to etch sub-micron features with high aspect ratios. The term xe2x80x9cTCPxe2x80x9d represents xe2x80x9ctransformer coupled plasma,xe2x80x9d purportedly a spatially uniform plasma, the apparatus for establishing such being disclosed in U.S. Pat. No. 5,731,565, assigned to Lam Research Corporation of Fremont, Calif. In contrast to the IPS system, the TCP system employs low gas flows, as well as low operating pressures and temperatures. For example, total gas flow may be as low as 30 sccm, system pressure may range from 18-25 mTorr and the gas mixture may comprise 10-15 sccm of each of CHF3 (trifluoromethane), C2HF5 (pentafluoroethane), and CH2F2 (difluoromethane). Neither Ar nor CO is employed in the gas mixture. Power requirements are similar to, but slightly lower than, the IPS system, being about 1100 watts for the source and 950 watts bias. However, the top plate of the chamber of the TCP system has been observed to erode prematurely due to capacitive coupling during operation, and the TCP system also does not employ a fluorine scavenger in its etch chamber. The TCP system also does not employ silicon surfaces in the chamber; its inner surfaces consist of cooled Si3N4 (silicon nitride) maintained at about 20xc2x0 C. to 60xc2x0 C., heated Al2O3 (aluminum oxide) at about 200xc2x0 C. to 250xc2x0 C., and anodized aluminum. Significant sputtering of the aluminum occurs in the chamber; residues in the chamber consist primarily of aluminum and magnesium fluoride and graphitic carbon.
While the IPS system employs an adjustable, dual-antenna inductive source and bias power control to adjust etch results, the TCP system etch results are adjusted by variance in the single antenna source power and bias power.
The IPS and TCP systems demonstrate different responses to what would conventionally be described as identical variations in parameters. For example, in the IPS system, the BPSG etch rate is strongly dependent on variations in source power and is only weakly dependent on bias power variations. The TCP system exhibits the opposite behavior, in that in the TCP system, the BPSG etch rate is only weakly dependent on source power changes and is strongly dependent on bias power adjustments. Indeed, relatively simple responses like 0 bias deposition rates (i.e., turning off the bias power and measuring the thickness of material that is deposited on the wafer) may well show different dependence on process parameters such as gas flow rates or pressure. Consequently, each of the two systems does not manifest responses which would be significant or instructive in modifying or improving performance of the other.
As a general discussion of high density oxide etch tools, all such tools deposit approximately 2000 to 4000 angstroms per minute of fluorocarbon polymer on a wafer under etch conditions if the bias power is set to zero. This means that any surface that is not powered is exposed to a flux of depositing material (pre-polymer) that will deposit on the surface if nothing is done to prevent such deposition. It is known that several techniques may be employed to prevent such deposition which include:
1) Heating the surfaces to between about 200xc2x0 C. and 250xc2x0 C.
2) Bombarding the surfaces with energetic ions. The bias power does this with the wafer and is of such a high power that it causes etching to occur from the same flux of reactants, except that the ion energies are increased by the bias power (from about 20 electron volts to several hundred electron volts).
3) Bombarding the surfaces with ions, wherein the bombardment is driven by capacitive coupling of energy from the inductive coil and the plasma (this technique is used in the above-discussed TCP system).
4) Making the surfaces out of an easily etched material such as silicon dioxide.
With all of the high density oxide etch tools, deposition on reactor surfaces results in the necessity of cleaning after etching of each wafer (such as a cleaning by an oxygen plasma cleaning technique).
Some of the high density oxide etch tools have a substantial capacitive coupling between the source coil and the plasma. The above-described TCP system has strong coupling which results in chamber wear and affects the xe2x80x9cacross waferxe2x80x9d profile uniformity. However, this coupling can be controlled. The common assignee of the present invention has filed several patent applications including U.S. application Ser. No. 09/021,155 entitled xe2x80x9cMethod of Modifying an RF Circuit of a Plasma Chamber to Increase Chamber Life and Process Capabilitiesxe2x80x9d; Ser. No. 09/031,400 entitled xe2x80x9cApparatus for Improved Low Pressure Inductively Coupled High Density Plasma Reactorxe2x80x9d; and Ser. No. 09/020,696 entitled xe2x80x9cMethod and Apparatus for Controlling Electrostatic Coupling to Plasmas,xe2x80x9d regarding the control of this capacitive coupling. These applications are hereby incorporated herein by reference.
Some of the high density oxide etch tools have virtually no capacitive coupling between the source coil and the plasma. The above-described IPS system has virtually no such coupling. The conducting silicon roof on the IPS system acts as an electrostatic shield which eliminates electrostatic coupling between the source coil and the plasma. Thus, roof temperature is used to control the amount of deposition that occurs on the roof of the IPS system.
Some of the high density oxide etch tools use reactive surfaces to line the chamber walls or parts of the walls. The TCP system uses inert surfaces such as Al2O3 and Si3N4. The IPS system uses silicon and heats it to temperatures which are too high to permit deposition and can be high enough to scavenge free fluorine from the plasma.
In short, while significant strides have been made toward effecting high aspect ratio etching at sub-half micron levels, state-of-the-art technology has so far failed to provide an acceptable, relatively simple, easy to control process using existing equipment which will produce high aspect ratio structures that meet industry requirements in terms of top CD control and selectivity.
The present invention provides a process of managing the amount of deposition that occurs in an etch chamber during an etch. The present invention provides a process suitable for use with the Dielectric Etch IPS Centura(copyright) system for etching doped silicon dioxide in the form of BPSG and other doped and undoped dielectric films used in integrated circuit fabrication, including, without limitation, SiO2, TEOS, BSG, and PSG, employing a relatively simple gas mixture delivered at low flow rates and at relatively low process temperatures which avoids the risk of CO-associated Ni contamination of the system chamber and, consequently, the wafers processed therein. Moreover, the low temperatures permit the use of an etch gas mixture which substantially holds top CD, does not etch stop, and etches the nitride and anti-reflective films present in some circuit structures.
The inventive process employs two primary etchant gases: CHF3 and CH2F2. The gas flows are extremely low, on the order of between about 10 and 40 sccm, preferably about 20 sccm, of CHF3 and between about 10 and 40 sccm, preferably about 10 sccm, of CH2F2 for relatively low pressure processes (approximately 20 mTorr). For higher pressure processes (approximately 45 mTorr), higher flow rates of CHF3 and CH2F2 may be used. For example, CHF3 flows and CH2F2 flows may be as high as about 40 sccm. Finally, flows of Ar (less than about 100 sccm) can also be used at higher pressures (40 mTorr). Additional quantities, on the order of 10 sccm or less of other gases, such as C2HF5 and CF4 (carbon tetrafluoride), may be added. A variant of the inventive process employing only CHF3 during the last portion thereof has been found to be useful in providing a xe2x80x9cpunchxe2x80x9d or dimple at the contact bottom extending into the pristine substrate silicon under the oxide and other layers.
The system chamber temperature is defined and controlled at the roof over the wafer and the ring surrounding the wafer. The roof is preferably held at a temperature of between about 115xc2x0 C. and 150xc2x0 C., which allows some deposition to occur, but does not allow free fluorine scavenging to occur. In fact, since polymer resides on the roof at 150xc2x0 C., the roof is protected from free fluorine attack. The ring is preferably held at a temperature of between about 200xc2x0 C. and 250xc2x0 C. It is believed that the ring does some fluorine scavenging, as no deposit was observed on it. The temperature of the chuck supporting the wafer is maintained between about xe2x88x9210xc2x0 C. and +300xc2x0 C.
Chamber pressure is maintained at least at about  greater than 5 mTorr, and preferably xe2x89xa720 mTorr.
Source power to the chamber is maintained between about 750 and 2000 watts, at a ratio of about 4 to 1 between inner and outer antennae, and bias power at between about 600 to 1000 watts.
In the process of the present invention, deposition on the chamber walls strongly influences what happens to the etch process. The etch process, especially for high aspect ratio etching, is complex and the results at the bottom of the etch feature are affected by variables that have no measurable effect on surface etch rates. The etch process consists of the plasma generating reactive neutral and ionic species. These species will etch dielectrics if the ions possess sufficient energy which is supplied by the bias power at the wafer. The role of the deposition is to remove some species from the plasma. Usually the removal of species results in etch processes that become more selective and more prone to taper and etch stop.
In general, etch processes which work best in wafer fabrication occur under conditions which balance the simultaneous tendency to etch and deposit. For example, some etch profiles (contacts) have a sidewall polymer (where virtually no ion bombardment occurs) and most etch processes actually deposit some polymer on the silicon contact on the bottom of the contact at the end of the etch, even though the bottom surface is bombarded by ions during the over-etch.
The processes of the present invention utilize a low, active roof temperature to control the amount of polymer deposited out of the plasma. It has been found that the preferred etches of the present invention result in a slightly bowed aperture of contact profile at a temperature of about 115xc2x0 C. and a slightly tapered profile at a temperature of about 140xc2x0 C. The roof temperature of 140xc2x0 C. allows less deposition on the chamber walls, so that more polymer is present at the wafer and, thus, more selective etching occurs. It has been found that the preferred etch with a roof temperature of 155xc2x0 C. results in an inadequate etch Si3N4, but a roof temperature of 140xc2x0 C. etches Si3N4 quite well.
As previously discussed, it is preferable to operate the ring at a low temperature. It has been found that etch stop cannot be prevented at a high ring temperature (without using CO or losing CD control) and etch stop is not observed at a low ring temperature. The scavenging effect of low temperature ring is therefore minimized in the present invention. It is believed that even cooler ring temperatures than have been possible with the equipment used in the development of the present invention would give better management of deposition in the etch chamber.